Elenco Electronics MO-1251 Bedienungsanleitung PDF herunterladen (Seite 59)

100

+5-15V

RESET

ICI

40178

CLK

CLK ENABLE

DECODED

OUTPUTS

0 1

6 7

8 9

CLOCK

INPUT

IC3-c

4001B

CLK

IC2

40116

RESET

CLK

ENABLE

DECODED

OUTPUTS

1 2

6 7

I 1 I

I I

IC3-a

4001B

001µF

22K

IC3-b

4001B

FIG. 8 -THE 4017B CONNECTED for divide -by -17 operation.

be negated

via any one of the 40I7B's

DECODED OUTPUTS.

The

count

se-

quence is then re- started by pressing

reset button S I .

Figure 8

shows

how to connect a

pair of

4017B's

to provide 17 stages of

fully decoded outputs.

The clock

sig-

nal is simultaneously

fed to both IC's;

however, when the

count

below

10,

the

DECODED

OUTPUT

of ¡Cl is low,

which

forces the

CLOCK

ENABLE

of IC2

to be

set

high by INVERTER gate IC3

-c.

So IC2 is negated, meaning it's

not

influenced by

the clock

signals. When

the 10th

clock pulse arrives, the

DECODED

OUTPUT

of ICI goes high,

which

negates ICI; simultaneously.

the CLOCK ENABLE Of IC2 is driven IOW

by IC3 -c, thereby

asserting IC2; the

high that is already in DECODED

OUTPUT

o is immediately

toggled into DECODED

OUTPUT I

by the same 10th

clock

pulse.

Eventually,

the 17th clock pulse

ar-

rives, causing the DECODEDOUTPUT9

IC2 to go high.

That triggers the 15µs

monostable made from

IC3 -a and

IC3 -b, which

clears both counters to

their high DECODED

OUTPUT O states.

The

counting sequence then repeats

itself.

Note

that the DECODED OUTPUT 9

IC1, and

the DECODED OUTPUTS o

and

of IC2

are lost in the counting

action,

so the

circuit gives

maximum

of 17

usable

counting states. Any number

counts within the range

from IO to

can be

input of

IC3 -a to

the appropriate

DECODED OUTPUT

Of IC2.

IC1

40226

CLOCK

CLK

ENABLE

RESET

GND

DECODED

OUTPUTS

CO 12

FIG.

9-PINOUT DIAGRAM

THE 4022B

Octal

counter.

Counters in computers

Counters can be used in simple ap-

plications where it's necessary

merely

count a

number

input

pulses, or divide them by a fixed

ratio. Those are some of the relatively

common

applications. But

what

about more

complex timing applica-

tions? For example, dividers are

very

often used in all kinds of

computer

timing

circuits.

A master

clock

first

generates an overall synchronizing

signal. Dividers are then used to

de-

rive other

clock

speeds

needed

slower

sections of the computer -yet

still need

to be synchronized

with

the

master

clock. For example, if the

master

clock runs at l MHz, then

4017B

decade counter could be used

generate

a synchronous 100 -kHz

signal.

Octal counter

The 4022B is a synchronous octal

counter (divide -by -8) having eight

DECODED

OUTPUTS

(0 TO 7) that sequen-

tially

go high

the IC is clocked.

Fig. 9 shows the 4022B pinout di-

agram. For normal octal counting, the

RESET

and CLOCK ENABLE pins are tied

low, which

asserts the IC

for

count-

ing. The high

bit advances to the

DECODED OUTPUT on the rising edge of

the clocking pulse. The CARRY OUT

signal

completes 1 cycle for every 8-

clock cycles. Lastly, the IC has a

built -in Schmitt trigger

on its

CLOCK

ENABLE line,

which

renders it insen-

sitive to clock signal rise and

fall

times.

Synchronous up- counters

The 4026B

and

4033B are both

synchronous up- counters that have

circuitry for decoding and driving a

segment

common

-cathode LED

dis-

play. The output

drive currents,

how-

ever,

are limited

to only

a few mA.

Figure 10 shows the

pinout

diagram

of the 4026B.

special feature

of that

IC is the DISPLAY ENABLE IN and DISPLAY

ENABLE OUT

pins. If the DISPLAY

ENABLE

is held high, the display

will

function

normally.

When

the pin

pulled low, the display

will

16t

-V

CLK

ENABLE

RESET

DISPLAY

ENABLE

IC1

4026B

DECODED

OUTPUTS

d 9

f 6

CARRY

OUT

DISPLAY

ENABLE

OUT -

UNGATED

SEGMENT

OUT

LED SEGMENT

DESIGNATIONS

FIG.

10- PINOUT DIAGRAM OF

THE

4026B decade counter

with 7- segment

display driver

having DISPLAY ENABLE

control

(a), and LED -segment designa-

tions

(b).

1 2 ... 54 55 56 57 58 59 60 61 62 63 64 ... 99 100

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